As technology evolves into era of sub-micron, there is a desire to integrate various two-terminal device elements such as but not limited to memory elements with high speed logic circuit elements into a single chip or integrated circuit (IC) to form an embedded memory. An example of the two-terminal device element is a magnetic random access memory (MRAM) element which gains popularity in recent years. MRAM, for example, includes magnetic tunnel junction (MTJ) stack layers sandwiched between top and bottom electrodes or terminals. The MTJ stack layers are generally connected to interconnects in the interlevel dielectric (ILD) layer. Nevertheless, it is difficult to integrate the two-terminal device element with logic circuit element in a single chip since each of these elements has different requirements. For example, it is necessary to alter or change the logic processing steps to accommodate for the two-terminal device element. This undesirably complicates the manufacturing process and increases the manufacturing cost. Moreover, during integration, the reliabilities of the two-terminal elements such as memory elements may degrade due to process limitations which cause electrical shorts between the terminals of the two-terminal elements or between one of the terminal to the device layer of the two-terminal device elements.
Accordingly, it is desirable that the process of manufacturing two-terminal device element to be highly compatible with logic processing and it is also desirable to integrate the two-terminal device elements with logic devices into a single chip or IC in a reliable, simplified and cost effective way.